The invention relates to preparation of a seed layer for selective metal deposition, particularly to a process utilizing a laser for preparation of a seed layer for selective metal deposition, and more particularly to a process for preventing conductor shorting after electroplating laser written conductor lines on selected portions of the seed layer.
U.S. Pat. No. 5,098,526 issued Mar. 24, 1992 to A. F. Bernhardt is directed to a process for the creation of plated metal interconnects from the surface of an integrated circuit (IC) chip, down the side of the chip, to contacts on the underlying circuit board, with the conductors being formed on the vertical sides of the chips, as well as on horizontal surfaces. The process of the above-mentioned U.S. Patent utilizes a seed layer upon which metal can be selectively deposited with the seed layer being formed by directing laser energy onto layers of electrical insulating material and a metal causing melting and intermixing thereof in locations or areas where surface activation is desired, thus enabling the deposition of a selected metal on the thus activated areas.
While the process of the above-referenced patent has produced satisfactory seed layers for selective metal deposition, conductor shorting problems have occurred because there is in some instances insufficient insulation material to insulate the metal layer underneath the perimeter region of the conductors from subsequent electroplating causing shorting between the conductor lines. Thus, a means of protecting the exposed metal under the conductor perimeter from being electroplated is needed, while at the same time allowing the full electroplating of the laser written conductor lines of the above-referenced patent.
The above-mentioned need is satisfied by the present invention which provides an improved seed layer forming process which prevents conductor shorting due to electroplating.